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Title: Hardware/Standards/ISA - ISABUS Pinout Source: IBM PC/AT technical reference.
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ISABUS Pinout:(just ignore the 16-bit extension if you want the 8-bit bus):-) --TimAT I/0 CHANNEL (SYSTEM BUS) PINOUTSPin Signal Description Direction*-------------------------------------------------------------------------------A1 -I/0 CH CK I/0 channel check;active low=parity error InA2 SD7 Data bit 7 In/OutA3 SD6 Data bit 6 In/OutA4 SD5 Data bit 5 In/OutA5 SD4 Data bit 4 In/OutA6 SD3 Data bit 3 In/OutA7 SD2 Data bit 2 In/OutA8 SD1 Data bit 1 In/OutA9 SDO Data bit 0 In/OutA10 -I/0 CH RDY I/0 Channel ready; pulled low to lengthen memory cycles InAl1 AEN Address enable; active high when DMA controls bus outA12 SA19 Address bft 19 outA13 SA18 Address bit 18 outA14 SA17 Address bit 17 OutA15 SA16 Address bit 16 outA16 SA15 Address bit 15 outA17 SA14 Address bit 14 outA18 SA13 Address bit 13 OutA19 SA12 Address bit 12 OutA20 SA11 Address bit 11 OutA21 SA1O Address bit 10 outA22 SA9 Address bit 9 OutA23 SAS Address bit 8 OutA24 SA7 Address bit 7 OutA25 SA6 Address bit 6 outA26 SAS Address bit 5 OutA27 SA4 Address bit 4 OutA28 SA3 Address bit 3 OutA29 SA2 Address bit 2 OutA30 SA1 Address bit 1 outA31 SA0 Address bit 0 OutB1 GROUNDB2 RESET DRV Active high lo reset or Initialize system logic outB3 +5VdcB4 IRQ9 Interrupt request 9 InB5 -5VdcB6 DRQ2 DMA request 2 InB7 -12VdcB8 -CARD SLCTD Card selected; activated by cards In XT's slot J8 InB9 +12VdcB10 GROUNDB11 -MEMW Memory write OutB12 -MEMR Memory read Out B13 -IOW I/O write In/OutB14 -IOR I/O read In/OutB15 -DACK3 DMA acknowledge 3 OutB16 DRQ3 DMA request 3 InB17 -DACK1 DMA acknowledge 1 OutB18 DRQ1 DMA request 1 InB19 -REFRESH Refresh In/OutB20 CLOCK System clock (67 ns,6 or 8MHz);50% duty cycle Out B21 IRQ7 Interrupt request 7 InB22 IRQ6 Interrupt request 6 InB23 IRQ5 Interrupt request 5 InB24 IRQ4 Intertupt request 4 InB25 IRQ3 Interrupt request 3 InB26 -DACK2 DMA acknowledge 2 OutB27 T/C Terminal count: pulses high when DMA term count reached OutB28 ALE Address latch enable OutB29 +5VdcB30 OSC High-speed clock (70 ns, 14.31818Mhz),50%duty cycle OutB31 GROUND16-bit AT extension-------------------C1 SBHE System bus high enable (data available on SD8-15) In/OutC2 LA23 Address bit 23 (unlatched) In/OutC3 LA22 Address bit 22 (unlatched) In/outC4 LA21 Address bit 21 (unlatched) In/OutC5 LA20 Address bit 20 (unlatched) In/OutC6 LA19 Address bit 19 (unlatched) In/OutC7 LA18 Address bit 18 (unlatched) In/OutC8 LA17 Address bit 17 (unlatched) In/OutC9 -MEMR Memory read (active on all memory read cycles) In/OutC10 -MEMW Memory write (active on all memory write cycles) In/OutC11 SD08 Data bit 8 In/OutC12 SD09 Data bit 9 In/OutC13 SD10 Data bit 10 In/OutC14 SD11 Data bit 11 In/OutC15 SD12 Data bit 12 In/OutC16 SD13 Data bit 13 In/OutC17 SD14 Data bit 14 In/OutC18 SD15 Data bit 15 In/OutD1 -MEM CS16 Memory 16-bit chip select (1 wait, 16-bit memory cycle) InD2 -I/O CSI6 I/O 16-bit chip select (1 wait, 16-bit I/O cycle) InD3 IRQ10 Interrupt request 10 InD4 IRQ11 Interrupt request 11 InD5 IRQ12 Interrupt request 12 InD6 IRQ15 Interrupt request 13 InD7 IRQ14 Interrupt request 14 InD8 -DACK0 DMA acknowledge 0 Out D9 DRQO DMA request 0 InD10 -DACK5 DMA acknowledge 5 OutD11 DRQ5 DMA request 5 InD12 -DACK6 DMA acknowledge 6 OutD13 DRQ6 DMA request 6 InD14 -DACK7 DMA scknowledge 7 OutD15 DRQ7 DMA request 7 InD16 +5VdcD17 -MASTER Used with DRQ to gain control of system InD18 Ground *-From system boardNote:- All signals are at standard TTL levels. - Connector is a 62-pin edge connector with a secondary 36-pin edge connector. - A or C=component side of board; numbers start closest to rear panel of machine.Source:IBM PC/AT Technical Reference, pages 1-25 through 1-37
 

Source:

IBM

PC/AT

technical

reference.

http://home.concepts-ict.nl/~nctnico/docs/isabus.txt

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Source: IBM PC/AT technical reference.

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