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Title: Hardware/Components/Processors/x86 - The Pentium: An Architectural History of the World's Most Famous Desktop Processor, Part II Article treats trace cache, instruction window, P4 and Pentium-M developments, branch prediction. [Ars Technica] (July 26, 2004)
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The Pentium: An Architectural History of the World's Most Famous Desktop Processor (Part II): Page 1
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Ars File: CPU Theory & Praxis
IntroductionThe trace cacheThe P4's instruction windowBranch prediction on the P4The cost of x86 support on the Pentium 4The Pentium M: Intel gets back to basicsImproved branch predictionThe 90nm P4 a.k.a. Prescott: the Pentium 4's last gasp
The Pentium: An Architectural History of the World's Most Famous Desktop Processor (Part II)
By Jon Stokes |
Published: July 26, 2004 - 01:40AM CT
Introduction
Back when the P4 first came out, there was quite a bit of negativity toward the new design in the hardware enthusiast community. Initial benchmarks showed that its performance was clearly clock-for-clock worse than that of the P-III, which was to be expected given its much longer pipeline.
Poor benchmark performance aside, there were also quite a few technical criticisms of its radical new design, leveled with varying degrees of validity by everyone from programmers to technology pundits.
Perhaps the most common gripe about the Pentium 4's microarchitecture, called Netburst by Intel, was that its staggeringly-long pipeline was a gimmick — a poor design choice made for reasons of marketing and not performance and scalability. Intel knew that the public naively equated higher MHz numbers with higher performance, or so the argument went, so they designed the P4 to run at stratospheric clock speeds and in the process made design tradeoffs that would prove detrimental to real-world performance.
I was one of the original dissenters from this school of thought, and in my P4 vs. the G4e series I tried to make a plausible technical case for why the P4's designers had made some of the design decisions that they did. I ultimately managed to convince myself and not a few others that the P4's deeply pipelined design was, in fact, performance-driven and not marketing-driven.
That was then, and this is now. As it turns out, the P4 bashers were right. Revelations from former members of the P4's design team, as well as my own off-the-record conversations with Intel folks, all indicate that the P4's design was the result of a marketing-driven focus on
clock speeds at the expense of actual performance and scalability.
It's my understanding that this fact is pretty widely known within Intel, even though it's not publicly acknowledged. Furthermore, the P4's focus on
megahertz has made it especially vulnerable to the industry-wide problems that have accompanied the 90nm transition, with the result that the new P4 probably won't scale very well at all in terms of both clock speed and performance. But I'm not going to say any more about the 90nm P4 problems, because I've addressed those elsewhere.
We now know that that during the course of the P4's design, the design team was getting pressure from the marketing folks to turn out a chip that would give Intel a massive MHz lead over its rivals. The reasoning apparently went that MHz is a single number that the general public understands, and they know that, just like with everything in the world except for golf scores, higher numbers are somehow better.
In the present article, which is the conclusion of my architectural history of the Pentium line, we'll take a look at the P4's Netburst architecture and at the sacrifices that Intel made at the altar of MHz. We'll then look at the relatively new Pentium M, before finishing off with a look at Prescott. If you didn't catch the previous article, be sure to read it first.
The Pentium 4
Pentium 4 summary table
Introduction date: April 23, 2001
Process: 0.18 micron
Transistor Count: 42 million
Clock speed at introduction: 1.7GHz
Cache sizes: L1: ~16K instruction,16K data
Features: hyperthreading added in 2002
I'm not going to give a breakdown of the P4's massive 20-stage basic pipeline, because I've done that elsewhere, but I will make a few general remarks about the ways in which it differs from that of the P6 core. I'll also cover one of P4's most radical innovations: the trace cache.
The P4's basic approach
The Pentium 4's designers took the P6's 12-stage pipeline and sliced it up into finer increments. Each stage does much less work, but this allows the processor to run faster. In this way, the P4 translates clock speed directly into performance, which is one way to take advantage of Moore's Curves.
Actually, let me unpack the previous statement a bit to show you what I mean. The following scenario is a bit oversimplified, but it gets the basic point across.
Let's say that each stage of a 20-stage processor does half the amount of work per clock cycle as each stage of a 10-stage processor. So the 20-stage processor takes two clock cycles to do what the 10-stage processor does in one. This means that the 20-stage processor has to run twice as fast as the 10-stage processor if it wants to do the same amount of work in the same amount of time. Why would you do things this way? Well, if people want to buy processors with higher clock speeds, then why not? Besides, as transistors shrink you can switch them faster, which means that you can continue to scale the clock speed of the processor as your manufacturing process improves. So to adapt the familiar dot-com business plan parody, we might say that Intel's reasoning went something like:
process improvements
clock speed increases
profit!!!!
This plan works pretty well until the clock speed increases start to run out of gas... but let's not get ahead of ourselves.
If you read my article on Moore's Law (the principle that I now call "Moore's Curves") then you understand that there's more than one way to take advantage of shrinking transistor sizes and other types of process improvements. Increasing
clock speeds a la the P4 is one of them, but adding functionality is another. Instead of translating process improvements into
clock speed increases, the P4's competitors (e.g., AMD's Athlon) decided to turn them into performance-enhancing hardware. Adding functionality in the form of execution hardware, branch prediction hardware, cache, etc. is another way to turn process improvements into performance.
Actually, both the P4 and the Athlon do a little bit of both: they add hardware and they increase their
clock speed. The difference between the two designs is a matter of emphasis, with Intel emphasizing
clock speed increases and AMD emphasizing hardware increases.
Unfortunately for AMD there's no single magic number that sums up "performance as derived from various and sundry hardware improvements." This didn't stop AMD from trying to invent such a number, though. AMD debuted its performance rating system to mixed reviews from the tech community, but the company has stuck with the system and while its positive effects may be debatable it doesn't seem to have done them any real harm. In fact, Intel is now adopting an analogous system for similar reasons, but more on that later.
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